/**
 * Copyright (C) 2021 - 2031 O-Cubes Co., Ltd.
 */

/****************************************************************
 *  @file    mem_map_table.h
 *  @brief   EOCV100 memory map table
 *  @version v1.0
 *  @date    03. Apr. 2023
 ****************************************************************/

#ifndef __MEM_MAP_TABLE_H__
#define __MEM_MAP_TABLE_H__

#ifdef __cplusplus
extern "C" {
#endif

/**
 * SYSMem
 */
/* DMEM base address */
#define MEM_MAP_DMEM_BASE_ADDR                 (0x00200000UL)
/* IMEM base address */
#define MEM_MAP_IMEM_BASE_ADDR                 (0x00400000UL)
/* ROM base address */
#define MEM_MAP_ROM_BASE_ADDR                  (0x00480000UL)
/* FLASH base address */
#define MEM_MAP_FLASH_BASE_ADDR                (0x00500000UL)

/**
 * SUBSYS_CFG
 */
/* Secure engine data */
#define MEM_MAP_SEC_DATA_BASE_ADDR             (0x10000000UL)
/* Secure engine cfg */
#define MEM_MAP_SEC_CFG_BASE_ADDR              (0x10002000UL)
/* DMAC cfg */
#define MEM_MAP_DMAC_BASE_ADDR                 (0x10004000UL)
/* RTC cfg */
#define MEM_MAP_RTC_BASE_ADDR                  (0x10006000UL)
/* PMU base address */
#define MEM_MAP_PMU_BASE_ADDR                  (0x10007000UL)

/**
 * PERI_CFG Per0
 */
/* CRG cfg */
#define MEM_MAP_CRG_BASE_ADDR                  (0x10100000UL)
/* PCL cfg */
#define MEM_MAP_PCL_BASE_ADDR                  (0x10101000UL)
/* GPIO base address */
#define MEM_MAP_GPIO_BASE_ADDR                 (0x10102000UL)
/* TOPSC base address */
#define MEM_MAP_TOPSC_BASE_ADDR                (0x10103000UL)
/* Tsensor base address */
#define MEM_MAP_TSENSOR_BASE_ADDR              (0x10104000UL)

/**
 * PERI_CFG Per1
 */
/* System counter cfg */
#define MEM_MAP_SYSCNT_BASE_ADDR               (0x10110000UL)
/* Timer cfg */
#define MEM_MAP_TIMER_BASE_ADDR                (0x10111000UL)
/* WDT0 cfg */
#define MEM_MAP_WDT0_BASE_ADDR                 (0x10112000UL)
/* WDT1 cfg */
#define MEM_MAP_WDT1_BASE_ADDR                 (0x10113000UL)

/**
 * PERI_CFG Per2
 */
/* UART0 base address */
#define MEM_MAP_UART0_BASE_ADDR                (0x10120000UL)
/* UART1 base address */
#define MEM_MAP_UART1_BASE_ADDR                (0x10121000UL)
/* UART2 base address */
#define MEM_MAP_UART2_BASE_ADDR                (0x10122000UL)
/* UART3 base address */
#define MEM_MAP_UART3_BASE_ADDR                (0x10123000UL)
/* UART4 base address */
#define MEM_MAP_UART4_BASE_ADDR                (0x10124000UL)
/* I2C0 base address */
#define MEM_MAP_I2C0_BASE_ADDR                 (0x10125000UL)
/* I2C1 base address */
#define MEM_MAP_I2C1_BASE_ADDR                 (0x10126000UL)
/* SPI0 cfg */
#define MEM_MAP_SPI0_BASE_ADDR                 (0x10127000UL)
/* SPI1 cfg */
#define MEM_MAP_SPI1_BASE_ADDR                 (0x10128000UL)
/* SPI2 cfg */
#define MEM_MAP_SPI2_BASE_ADDR                 (0x10129000UL)
/* SPI3 cfg, XIP flash */
#define MEM_MAP_SPI3_BASE_ADDR                 (0x1012A000UL)

/**
 * MM
 */
/* Monitor cfg */
#define MEM_MAP_MONITOR_BASE_ADDR              (0x10200000UL)
/* Meter cfg */
#define MEM_MAP_METER_BASE_ADDR                (0x10202000UL)

/*Saradc cfg*/
#define MEM_MAP_SARADC_BASE_ADDR               (0x10203800UL)
/*Sdadc cfg*/
#define MEM_MAP_SDADC_BASE_ADDR                (0x10203C00UL)

/**
 * RCPU
 */
/* TCIP cfg */
#define MEM_MAP_TCIP_BASE_ADDR                 (0xE0000000UL)

#ifdef __cplusplus
}
#endif

#endif /* __MEM_MAP_TABLE_H__ */

